3D Near-Memory LPU
Inference is stalling on memory, not on math.
Token generation reads the entire model out of memory once per token. That makes decode a bandwidth problem, and bandwidth is where accelerators are starved. Wahid stacks DRAM vertically on the compute unit to target 10–40 TB/s — HBM-class capacity, well above HBM’s bandwidth ceiling.
Silicon this team has already put into volume production. Verifiable today.
Physics or market conditions that hold regardless of whether Wahid succeeds.
A design goal for unbuilt hardware. Not measured, not independently verified.
Decode reads the whole model, once per token.
Inference has two phases with opposite appetites, and almost every accelerator is sized for the wrong one.
Digesting the prompt is compute-hungry
The whole prompt can be processed in parallel, so the arithmetic units stay busy. This phase sets time-to-first-token, and it is bound by FLOPS.
Emitting the answer is memory-hungry
Each token must stream every model weight out of memory before the next one can start. Adding FLOPS does not speed that up. Only bandwidth does.
Long contexts, multi-turn memory and large KV caches push the balance further toward decode. This is why an accelerator can hold a large nominal FLOPS number and still generate tokens slowly: the arithmetic units spend most of their time waiting on memory.
Every existing memory technology gives something up.
LPDDR is cheap and roomy but too slow. HBM is fast but expensive, supply-constrained and capacity-limited. SRAM is extremely fast and far too small, forcing large clusters to hold one model. The gap is a technology with HBM-class capacity, well above HBM bandwidth, at a manufacturable cost.
| Memory | Reference system | Bandwidth | Capacity | Cost | Limiting factor |
|---|---|---|---|---|---|
| DDR / LPDDR | DGX Spark | 273 GB/s | 128 GB | Low | Bandwidth |
| HBM | Ascend 950DT | 4 TB/s | 144 GB | High | Cost, supply |
| SRAM | Groq LPU | 150 TB/s | 500 MB | Very high | Capacity |
| 3D DRAM | Wahid Enlight | 10–40 TB/s | 20–80 GB | Medium | Integration difficulty |
Source: company business plan, August 2026. Reference systems named by the company. The 3D DRAM row is a design target, not a measured device.
Stack the memory on the compute unit, then design the compute around the dataflow.
2, 4 or 8 DRAM layers
Through-silicon vias replace side pins, opening parallel read and write channels across every layer and shortening the signal path.
Bumpless Cu-to-Cu
Wafer-to-wafer and die-to-wafer hybrid bonding at 1 µm interconnect pitch, with no auxiliary wafer required.
Standard DDR protocol
The stack presents a mature DDR interface, so it drops into existing system architectures without a hardware rewrite.
Over 80% multi-core scaling
KV-cache compression cuts memory use by more than 60%, with 4-bit quantisation supported natively in hardware.
This team has already put 3D DRAM into mass production.
The bandwidth claim rests on execution history rather than on a paper design. The founding team, out of Nano Labs (NASDAQ: NA), has shipped 3D DRAM compute silicon commercially — including a mass-produced accelerator with a 6,144-channel 3D DRAM subsystem rated at 24 TB/s across 192 cores.
6 / 7 / 12 / 22 / 40 nm
Dedicated IC designs, plus custom DRAM memory chips at 38, 25 and 20 nm.
6,144 channels at 24 TB/s
A mass-produced accelerator with 192 compute cores on a 2D-torus network, already validated in volume.
Tier-one foundry relationships
Established partnerships with leading foundries and a diversified supplier base.
Two form factors: a desktop appliance and a data-centre card.
Both are built on the same 3D + 2D heterogeneous memory architecture — a fast stacked tier for the working set, a large conventional tier behind it. The specifications below are design targets from the business plan. No silicon exists yet.
Enlight-LPU 1D
Local, offline large-model inference for private and edge deployment.
- Compute
- 512 TFLOPS
- 3D memory
- 10 TB/s · 10–80 GB
- 2D memory
- 300 GB/s · 8–64 GB
- Power
- 50–100 W
- Data types
- BF16 / FP16 / FP8 / FP4 / INT
- Host
- PCIe 6.0
- Model support
- 200B on a single chip
Enlight-LPU 4D
Standard server card for private model clusters and API serving.
- Compute
- 2,000 TFLOPS @FP8
- 3D memory
- 40 TB/s · 40–320 GB
- 2D memory
- 1,200 GB/s · up to 256 GB
- Power
- 500 W
- Target price
- $10,000 per card
- Host
- PCIe 6.0
- Model support
- All mainstream open-source models
Desktop decode throughput — Llama 3 70B
Tokens per second at FP4 · higher is better
| Desktop class | FP8 TFLOPS | 3D DRAM | LPDDR | Bandwidth | Decode TPS |
|---|---|---|---|---|---|
| NVIDIA Spark GB10 | 250 | — | 128 GB | 273 GB/s | 5 |
| Mac Studio M3 Ultra | n/a | — | 96–128 GB | 819 GB/s | 16 |
| AMD Ryzen AI Max+ 395 | 75 + 50 | — | 128 GB | 256 GB/s | 5 |
| Enlight-LPU 1D | 512 | 40 GB | 64 GB | 10,000 GB/s | 200 |
Source: company business plan, August 2026. Competitor figures are vendor specifications as cited by the company; the Enlight-LPU row is a design target. Neither has been independently benchmarked.
Meet the frameworks people already run.
Inference silicon fails on ecosystem more often than on hardware. The stack targets the serving frameworks teams deploy today rather than asking them to port to a proprietary runtime.
Semiconductor operators, not first-time chip builders.
Stanley Wu
- CTO of Lombard Finance, building trust-minimised Bitcoin infrastructure
- Co-founder and CTO of Ankr, a leading Web3 infrastructure platform
- Over a decade at Amazon as Senior Software Engineer and Tech Lead, working on distributed systems at scale
- M.S. in Computer Science, University of Rochester; B.S., Shanghai Jiao Tong University
Thomas Hu
- Co-founder and former CEO of Nano Labs (NASDAQ: NA)
- 20 years in semiconductor R&D and management; formerly at Trident, Amlogic and Entropic
- Leading IC Talent, Ministry of Industry and Information Technology
- Master’s degree, Shanghai Jiao Tong University
Bob Li
- Former CTO of Nano Labs; 20 years in chip R&D and management
- Led multiple 3D DRAM compute chips from design through tape-out to mass production
- Former technical leader at Trident, Hangzhou Guoxin and Guoke Micro
- PhD in Information and Communication Engineering, Zhejiang University
Luo Chengping
- Leads chip architecture design
- Former core GPU architect at Biren, Hygon and Qualcomm
- 24 years of GPU performance optimisation
- Former senior R&D architecture executive at Trident and MediaTek
Wang Qi
- Former Dean of the Nano Labs Research Institute
- Former Director of the Innovation Business Unit at Beijing Jianan Jiesi
- Former technical planning expert at Huawei
- PhD in Computer Science, Nottingham Trent University
Shi Bin
- Leads software design
- Former Software Director at Nano Labs
- Former Director of Beijing Jianan Jiesi Software
- Former senior engineer at iQiyi and R&D manager at Huaxia Vision
First silicon is ahead, not behind.
Nothing on this page has been measured on an Enlight device. The plan of record runs from tape-out to volume production inside 2027, with EL200 and EL300 generations following through 2030.
Tape-out
Design frozen and released to the foundry.
Fab out
First wafers complete, stacking and bonding validated.
Engineering samples
The first point at which third-party benchmarking becomes possible.
Mass production
Volume ramp of the EL100 generation.
What a technical reviewer should ask us for.
These are the four places where this company could be wrong. We would rather you arrive with them already in hand.
01Sustained versus internal bandwidth
The 10–40 TB/s figure needs to be specified as bandwidth delivered to the compute units under continuous decode, not aggregate bandwidth inside the stack.
02Prefill and time-to-first-token
The comparisons on this page are decode throughput. Long-context prefill is compute-bound and is not characterised here.
03Yield and cost at 4–8 layer stacking
Bonding yield drives unit cost, and unit cost drives the $10,000 card target.
04Independent benchmarks
No MLPerf Inference result or third-party measurement exists, and none can until engineering samples in late 2027.